1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and, more particularly, to a flash memory.
2. Description of the Related Art
A nonvolatile semiconductor memory, e.g., a NAND-type flash memory is mainly constituted by a memory cell array and a peripheral circuit disposed around the memory cell array.
For example, the gate electrode of a memory cell transistor provided in the memory cell array region is connected to a row decoder circuit through an interconnect line region.
In the boundary between the memory cell array region and interconnect line region, dummy cells that do not function as a memory cell are provided within a region neighboring the terminal end of the memory cell array (refer to e.g., Jpn. Pat. Appln. Publication No. 2004-342261).
If the periodicity of the pattern is distorted in the region neighboring the terminal end of the memory cell array including the dummy cells having the same configuration as that of the memory cell array region, a pattern collapse occurs at process time. In order to prevent the occurrence of the pattern collapse, the region neighboring the terminal end of the memory cell array is designed such that the row direction width thereof becomes larger than that of the memory cell array region. Assuming that design rule F is applied to the active area of a memory cell transistor in terms of the row direction width, design rule of 3F or more is applied to the active area of the region neighboring the memory cell array.
The memory cell transistor provided in the memory cell array region has a three-dimensional floating gate structure in which the upper surface and side surfaces of a floating gate electrode are covered by a control gate electrode through an inter-gate insulating film.
However, as described above, the row direction width of the active area is large in the region neighboring the terminal end of the memory cell array. Therefore, the area in which the control gate electrode covers the side surfaces of the floating gate electrode is smaller than the area in which it covers the upper surface of the floating gate electrode. Accordingly, the area in which the floating gate electrode and control gate electrode are opposed to each other becomes larger than that in the memory cell array region, with the result that the floating gate electrode becomes close to a two-dimensional floating gate structure.
Therefore, two-dimensional effect becomes increased in the gate electrode in the region neighboring the terminal end of the memory cell array, which increases the capacitance between the control gate electrode and floating gate electrode, with the result that the coupling ratio of the dummy cell is decreased. It follows that when a write voltage is applied to a word line which is shared by a memory cell and dummy cell, a voltage applied to an inter-gate insulating film interposed between the control gate electrode and floating gate electrode in the dummy cell becomes higher than that in the memory cell.
When the inter-gate insulating film is broken down by the application of the write voltage, the write voltage is applied only to a tunnel oxide film to thereby cause a short-circuit between the gate electrode and a semiconductor substrate.
To avoid this, a method can be considered where the oxide film formed on the substrate in the region neighboring the terminal end of the memory cell array is thicker than that of in the memory cell array region. In this case, however, an area for forming the thick oxide film is required to increase the size of the memory cell array region to form transition area.